With regard to nonvolatile read/write memories, investigations are increasingly be made relating to memory cell configurations in which magnetoresistive elements are used for storing information.
Experts understand that a magnetoresistive element, also called a magnetoresistance element, is a structure that has at least two ferromagnetic layers and a non-magnetic layer arranged in between. Depending on the construction of the layer structure, a distinction is made between a GMR (Giant Magnetoresistance) element, a TMR (Tunneling Magnetoresistance) element and a CMR (Colossal Magnetoresistance) element (see S. Mengel, Technologieanalyse Magnetismus, Band 2, XMR-Technologien [Technology analysis magnetism, volume 2, XMR technologies], published by VDI Technologiezentrum Physikalische Technologien, August 1997).
The term GMR element is used for layer structures that have at least two ferromagnetic layers and a non-magnetic, conductive layer arranged in between and that exhibit the so-called GMR (Giant Magnetoresistance) effect. The GMR effect is understood to refer to the fact that the electrical resistance of a GMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented parallel or anti-parallel to one another. The GMR effect is large in comparison with the so-called AMR (Anisotropic Magnetoresistance) effect. The AMR effect is understood to refer to the fact that the resistance in magnetized conductors is different parallel and perpendicular to the magnetization direction. The AMR effect is a bulk effect that occurs in ferromagnetic monolayers.
The term TMR element is used by experts for xe2x80x9cTunneling Magnetoresistancexe2x80x9d layer structures that have at least two ferromagnetic layers and an insulating, non-magnetic layer arranged in between. In this case, the insulating layer is so thin that a tunneling current arises between the two ferromagnetic layers. These layer structures likewise exhibit a magnetoresistive effect brought about by a spin-polarized tunneling current through the insulating, non-magnetic layer arranged between the two ferromagnetic layers. In this case, too, the electrical resistance of the TMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented parallel or anti-parallel to one another. In this case, the relative change in resistance is about 6 to 40% at room temperature.
It has been proposed (see, for example, D. D. Tang et al. IEDM 95, pages 997 to 999, J. M. Daughton, Thin Solid Films, Vol. 216 (1992), pages 162 to 168, Z. Wang et al, Journal of Magnetism and Magnetic Materials, Vol. 155 (1996), pages 161 to 163) to use GMR elements as memory elements in a memory cell configuration. The memory elements are connected in series using read lines. Word lines run transversely with respect to the read lines and are insulated both from the read lines and from the memory elements. Signals applied to the word lines cause a magnetic field as a result of the current flowing in each word line. This magnetic field, given sufficient strength, influences the magnetizations of the memory elements situated underneath. For writing information, x/y lines are used, which cross at the memory cell to be written to. Signals are applied to the x/y lines, and at the crossover point, these signals cause a magnetic field which is sufficient for the magnetization reversal. In this case, the magnetization direction is reversed in one of the two ferromagnetic layers. By contrast, the magnetization direction in the other of the two ferromagnetic layers remains unchanged. The magnetization direction in the last-mentioned ferromagnetic layer is fixed by using an adjacent antiferromagnetic layer that fixes the magnetization direction, or by increasing the switching threshold of the ferromagnetic layer through different material or different dimensioning, for example, a different layer thickness, in comparison with the first-mentioned ferromagnetic layer. For reading out the information, a pulsed signal is applied to the word line, and this pulsed signal switches the relevant memory cell back and forth between the two magnetization states. The current through the bit line is measured, from which the resistance of the corresponding memory element is determined.
U.S. Pat. No. 5,173,873 discloses a magnetoresistive memory cell configuration in which transistors are provided for selecting the memory cells that will be read.
U.S. Pat. No. 5,640,343 discloses a memory cell configuration in which TMR elements that are connected in series with a diode are used as memory elements. The diode serves for reading out the information of the individual memory cells.
It is accordingly an object of the invention to provide a memory cell configuration having magnetoresistive elements and a method for operating the memory cell configuration which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a memory cell configuration having magnetoresistive elements in which the stored information can be reliable read-out.
It is also an object of the invention to construct the memory cell configuration with a high packing density and with a low outlay on process engineering.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration that includes: a signal line; and memory cells. Each one of the memory cells has two magnetoresistive elements. The two magnetoresistive elements of each one of the memory cells are magnetized to have different resistances. The signal line connects the two magnetoresistive elements of one of the memory cells in series to form an overall resistor with two ends. One of the two ends of the overall resistor is connected to a first voltage having a magnitude and a polarity. Another one of the two ends of the overall resistor is connected to a second voltage having a magnitude equal to the magnitude of the first voltage and a polarity opposite the polarity of the first voltage.
In accordance with an added feature of the invention, each one of the two magnetoresistive elements of each one of the memory cells is either a Giant Magnetoresistance element or a Tunneling Magnetoresistance element.
In accordance with an additional feature of the invention, the two magnetoresistive elements of one of the memory cells are configured adjacent to one another in a plane.
In accordance with another feature of the invention, there is provided a plurality of first lines running parallel to each other; and a plurality of second lines running parallel to each other. The plurality of the first lines and the plurality of the second lines cross each another. The two magnetoresistive elements of each one of the memory cells are connected between one of the plurality of the first lines and one of the plurality of the second lines. The two magnetoresistive elements of one of the memory cells are connected to different ones of the plurality of the first lines and to the same one of the plurality of the second lines.
In accordance with a further feature of the invention, each one of the two magnetoresistive elements of each one of the memory cells includes at least a first ferromagnetic layer element, a nonmagnetic layer element, and a second ferromagnetic layer element. The nonmagnetic layer element is configured between the first ferromagnetic layer element and the second ferromagnetic layer element. In each one of the memory cells, the first ferromagnetic layer element and the second ferromagnetic layer element of a first one of the two magnetoresistive elements have magnetizations that are oriented parallel to each other. In each one of the memory cells, the first ferromagnetic layer element and the second ferromagnetic layer element of a second one of the two magnetoresistive elements have magnetizations that are oriented anti-parallel to each other.
In accordance with a further added feature of the invention, the first ferromagnetic layer element and the second ferromagnetic layer element of each one of the two magnetoresistive elements of each one of the memory cells includes at least one of the following elements: Fe, Ni, Co, Cr, Mn, Bi, Gd and Dy. The first ferromagnetic layer element of each one of the two magnetoresistive elements of each one of the memory cells has a thickness between 2 nm and 20 nm perpendicular to the layer plane. The second ferromagnetic layer element of each one of the two magnetoresistive elements of each one of the memory cells has a thickness between 2 nm and 20 nm perpendicular to the layer plane. The nonmagnetic layer element of each one of the two magnetoresistive elements of each one of the memory cells includes at least one of the following materials: Al2O3, NiO, HfO2, TiO2, NbO, SiO2, Cu, Au, Ag and Al. The nonmagnetic layer element of each one of the two magnetoresistive elements of each one of the memory cells has a thickness between 1 nm and 5 nm.
In accordance with a further additional feature of the invention, there is provided, a plurality of lines; and a plurality of current followers. Each one of the plurality of the current followers is connected to a respective one of the plurality of the lines.
In accordance with yet an added feature of the invention, there is provided, a plurality of first lines running parallel to each other; a plurality of second lines running parallel to each other; and a plurality of current followers. Each one of the plurality of the current followers is connected to a respective one of the plurality of the second lines. The plurality of the first lines and the plurality of the second lines cross each another. The two magnetoresistive elements of each one of the memory cells are connected between one of the plurality of the first lines and one of the plurality of the second lines. The two magnetoresistive elements of one of the memory cells is connected to different ones of the plurality of the first lines and to a given one of the plurality of the second lines.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for operating a memory cell configuration, which includes a step of: providing a memory cell configuration that includes: a signal line; and memory cells; each one of the memory cells having two magnetoresistive elements; in each one of the memory cells, the two magnetoresistive elements are magnetized to have different resistances; the signal line connecting the two magnetoresistive elements of one of the memory cells in series to form an overall resistor with two ends; one of the two ends of the overall resistor being connected to a first voltage having a magnitude and a polarity; and another one of the two ends of the overall resistor being connected to a second voltage having a magnitude equal to the magnitude of the first voltage and a polarity opposite the polarity of the first voltage. The method also includes steps of: reading out information from the one of the memory cells by assessing whether a voltage drop on the signal line is greater than or less than zero; and changing the information stored in the one of the memory cells by changing the resistances of both of the magnetoresistive elements of the one of the memory cells.
The memory cell configuration has memory cells, each memory cell containing two magnetoresistive elements. TMR elements or GMR elements are preferably used as magnetoresistive elements since they exhibit sufficiently large changes in resistance in the event of magnetization reversal at room temperature, and at the same time, can be subjected to magnetization reversal with tenable magnetic fields.
This memory cell configuration makes it possible to store data using multi-level logic, that is to say, in a memory cell, four different states are possible with regard to the resistances of the magnetoresistive elements. These states can be assigned to four different logic values. An increased memory density and hence packing density can thereby be achieved.
As an alternative, the magnetoresistive elements in each memory cell can be magnetized in such a way that they always have different resistances. In this case, two different states are possible per memory cell, which states can be assigned to two logic values. This configuration of the memory cell configuration can be read with a reduced outlay on circuitry, so that the memory cell configuration can be produced with a reduced space requirement. In addition, this configuration enables higher security during read-out.
In order to read from this memory cell configuration, the magnetoresistive elements of a memory cell are preferably in each case connected between a voltage level and a signal line, the voltage level having the same magnitude for both magnetoresistive elements, but having a different polarity. The signal line is the same for both magnetoresistive elements. It is assessed, whether the voltage drop on the signal line is greater than or less than zero. Consequently, a simple bridge circuit is sufficient for reading out the information.
In this case, it is advantageous to arrange the magnetoresistive elements of a memory cell adjacent to one another. In this way, technologically governed property inhomogeneities of the magnetoresistive elements that are based on systematic process inhomogeneities, in particular during the deposition, lithography, etching, etc. will have no influence on the assessment signal. Furthermore, the external circuitry required for the bridge circuit is symmetrical.
The memory cell configuration can be assessed both by switching read-out and by non-switching read-out. Non-switching read-out, which is faster and simpler to realize than switching read-out, is understood to be the fact that the currents in the interconnect grid are subcritical during the read-out operation, that is to say, the switching thresholds for the magnetization reversal of the memory elements are not reached. The memory cell states remain unchanged, with the result that the original memory information does not have to be read in again in a time-consuming manner after the read-out.
In this memory cell configuration, the different logic states that are assigned to zero and one are identified by the different sign of the read signal. Signals with different signs can easily be distinguished by circuitry. Therefore, the memory cell configuration can be read with high assessment security.
With regard to a large-area memory cell configuration, it is advantageous to provide first and second lines. In this case, the first lines run parallel to one another and the second lines run parallel to one another. The first lines cross the second lines. The magnetoresistive elements are in each case connected between one of the first lines and one of the second lines. In this case, the magnetoresistive elements of one of the memory cells are in each case connected to two different first lines and the same second line. In order to read out the information stored in the memory cell, voltage levels which have the same magnitude but opposite polarity are applied to the two first lines, and the remaining first lines are connected to reference potential, in particular ground. On the second line, which is connected to the magnetoresistive elements of the selected memory cell, the signal is assessed. The voltage signal generated on the second line has a different polarity depending on the stored information. The signal level is dependent on the magnetoresistance values of the magnetoresistive elements, on the voltage levels applied to the first lines, and on the number of first lines present. As the number of first lines increases, the level of the signal decreases.
In order to compensate for the influence of the number of first lines on the signal level, it is advantageous to connect the second lines to a current follower. The current follower has a feedback operational amplifier whose inverting input is connected to the respective second line. The non-inverting input is connected to ground potential. As a result, the potential on the second line is regulated to zero. At the output of the operational amplifier, a signal is present from which the polarity of the output signal of the memory cell configuration can be read.
Preferably, the magnetoresistive elements each have at least a first ferromagnetic layer element, a nonmagnetic layer element, and a second ferromagnetic layer element. The nonmagnetic layer element is arranged between the first ferromagnetic layer element and the second ferromagnetic layer element. For each memory cell, the magnetizations in the first ferromagnetic layer element and the second ferromagnetic layer element are oriented parallel to one another in one of the magnetoresistive elements and the magnetizations in the first ferromagnetic layer element and the second ferromagnetic layer element are oriented antiparallel to one another in the other of the magnetoresistive elements.
It lies within the scope of the invention for the first ferromagnetic layer element and the second ferromagnetic layer element to contain at least one of the materials Fe, Ni, Co, Cr, Mn, Bi, Gd and/or Dy, and for them to have in each case a thickness of between 2 and 20 nm perpendicular to the layer plane.
It lies within the scope of the invention for the non-magnetic layer element to contain Al2O3, NiO, HfO2, TiO2, NbO, SiO2, Cu, Au, Ag and/or Al, and to have a thickness of between 1 nm and 5 nm perpendicular to the layer plane.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration and method for operating the configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.